As part of my reconfigurable computing class, I designed an image processing accelerator capable of applying effects to an image sent from an external device. It was created using a mix of Xilinx provided IP and self-written IP. The image pixel data was sent to the FPGA over a UART to AXI4-Stream interface written by hand. Before getting passed to the image controller, the UART data was buffered in an AXI-Stream FIFO so any pipeline stalls created in the image processor didn't cause any packet drops in the UART receiver IP. The image processor took the AXI-Stream pixel data, converted it to AXI4-Lite, before using vendor IP to send and recieve data to the onboard DDR memory. Image effects were applied by sending commands over the UART bus to the image processor, which was able to read pixel data from memory, apply effects, and write the modifed data back to the system memory.
Similar to my other school projects, I can't share the code for this because of RIT's acadmic honesty policies. Sorry :(
January 1st, 1970