As part of my Digital Systems Design II class at R.I.T., I designed and synthesized a five stage pipelined MIPS CPU from the ground up at the behavioral level in VHDL.

The CPU was developed using Xilinx Vivado, and the code was tested and synthesized on a Xilinx Artix-7 FPGA on a Digilent Basys 3 development board.

Note: Due to this being a college class, I am unable to post code publicly because I do not want to infringe upon my University's Academic Honestly policies.

However, if you would like a better idea of what goes on in this project, you can download the manual that goes over the lab exercises here.

If you would like to view some of the code from this project contact me privately and I can provide some of my source code.

January 14th, 2019

No updates yet

Sorry :(